Cutting-Edge Hazard3 Core Utilizing RISC-V Architecture Developed by Sole Designer, Now Implemented in Real Chip RP2350

After Raspberry Pi unveiled the RP2350 chip, one of its features is the Hazard3 core. This core was designed by Luke Wren, an engineer at Raspberry Pi. Hazard3 is a reduction of Hazard5, previously designed by Luke. The design focuses on simplicity due to its operation in just 3 steps. This core implements the RV32I instruction set along with another set of instructions such as integer multiplication instructions, atomic memory unit instructions, data compression instructions, and bit manipulation instructions. The design process took less than a week after forking the code from Hazard5.

For those interested, they can compile the CPU into an FPGA for experimentation. Luke tested this CPU with ULX3S board ($145) and iCEBreaker board ($79.95). The code is licensed under Apache 2.0, making it usable in almost any format.

RISC-V architecture is simply an instruction set architecture that requires the implementation of various instructions as circuits. Some designs may be closed-source. The widespread use of Hazard3 is due to its integration with the RP2350 chip and its availability for other uses. This presents an opportunity for an increased use of software for RISC-V CPUs.

TLDR: Raspberry Pi introduced the RP2350 chip with the Hazard3 core designed by Luke Wren. It offers simplicity in operation, implements RV32I instructions, and opens up possibilities for RISC-V software usage.