AMD has unveiled Data Processing Unit (DPU) chips to meet the challenges of AI server networks, splitting operations into two parts: Front-end for data exchange between AI clusters and Backend for managing data between accelerators and servers.
The DPU chip for Front-end tasks is the AMD Pensando Salina and AMD Pensando Pollara 400 for Backend operations. The AMD Pensando Salina DPU, the third generation of DPU chips, performs twice as well as its predecessor, supporting a throughput of up to 400G.
Meanwhile, the AMD Pensando Pollara 400 is the first DPU chip based on the Ultra Ethernet Consortium (UEC) standard and designed on AMD’s P4 architecture. It improves load balancing, accelerates handling of lost packets, and swiftly troubleshoots networks with issues.
Both the AMD Pensando Salina DPU and AMD Pensando Pollara 400 are undergoing testing with customers in the fourth quarter of this year and will be available for general distribution in the first half of 2025.
TLDR: AMD introduces DPU chips for AI server networks, with improved performance and capabilities for data processing tasks, set to be available for general distribution by early 2025.
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